The present invention relates to CCD imagers.
One key driving parameter in CCD imagers is the noise. A CCD imager with improved signal-to-noise ratio will have better image quality, better dynamic range, and better low-light performance.
The prior art normally uses a very simple sense amplifier on chip with the CCD array for charge detection; for example, a simple source follower stage is commonly used. The output of the simple charge detection amplifier will then be sent off chip for processing by a more complicated amplifier, such as a correlated double sampler.
By contrast, the present invention teaches a CCD imager with one or more correlated-clamp-sample-and-hold amplifiers on chip. (This amplifier functions very similarly to the correlated double sampling amplifiers of the prior art.) This structure is itself believed to be novel, and moreover the amplifier configuration preferably used includes a number of other novel features.
Integrating a correlated-clamp-sample-and-hold amplifier with a CCD imager results in at least two major advantages: first, noise is reduced, simply because the signal driven off chip is not low level, but has already been converted to a reasonable level.
Second, on-chip processing eliminates problems with timing which can result from pulse delays introduced in the logic in the CCD driver circuits. Temperature-dependent variations and power-supply sensitivity of these delays make them somewhat unpredictable, and since it is difficult to acquire synchronization of a data stream at video rates, off-chip video signal processing can be quite a difficult task. The present invention avoids this problem.
Third, another particular advantage of integrating a correlated-clamp-sample-and-hold amplifier on-chip is that a dummy charge-sensing node which has essentially the same topography as the active charge-sensing node can be used to provide a reference input to the amplifier which minimizes the reset noise contributed by the primary charge-sensing node. Since the active and dummy nodes are integrated in the same monolithic semiconductor layer, better matching of their characteristics is assured, and therefore better noise cancellation will be attained.
A further related advantage of using a dummy charge-sensing node on-chip is that the dummy node and the active charge-sensing node can be connected to the same on-chip reference voltage generator, avoiding any mismatch in this respect.
According to the present invention, there is provided: A CCD structure comprising: a chain of CCD wells; a first charge-sensing node coupled to one end of said chain of CCD wells; clocking means for clocking charge packets from said end of said chain of CCD wells into said first charge-sensing node; a buffer amplifier connected to sense the voltage on said first charge-sensing node; reset means for resetting said charge-sensing node to a predetermined potential; a dummy charge-sensing node, said dummy node being topologically similar to and integrated in a common body of monocrystalline semiconductor material with said first charge-sensing node; and means for sensing the voltage change on said first charge-sensing node (which occurs after a charge packet has been transferred into said first charge-sensing node) with reference to the voltage on said dummy node.